/** * @file xmc1_eru_map.h * @date 2019-07-30 * * @cond ***************************************************************************** * XMClib v2.2.0 - XMC Peripheral Driver Library * * Copyright (c) 2015-2020, Infineon Technologies AG * All rights reserved. * * Boost Software License - Version 1.0 - August 17th, 2003 * * Permission is hereby granted, free of charge, to any person or organization * obtaining a copy of the software and accompanying documentation covered by * this license (the "Software") to use, reproduce, display, distribute, * execute, and transmit the Software, and to prepare derivative works of the * Software, and to permit third-parties to whom the Software is furnished to * do so, all subject to the following: * * The copyright notices in the Software and this entire statement, including * the above license grant, this restriction and the following disclaimer, * must be included in all copies of the Software, in whole or in part, and * all derivative works of the Software, unless such copies or derivative * works are solely in the form of machine-executable object code generated by * a source language processor. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * To improve the quality of the software, users are encouraged to share * modifications, enhancements or bug fixes with Infineon Technologies AG * at XMCSupport@infineon.com. ***************************************************************************** * * Change History * -------------- * * 2015-02-20: * - Initial version * * 2015-08-25: * - Added support for XMC1400 devices * * 2019-07-30: * - Added support for XMC1404-Q040 * * @endcond */ #ifndef XMC1_ERU_MAP_H #define XMC1_ERU_MAP_H /********************************************************************************************************************* * MACROS *********************************************************************************************************************/ #define ERU0_ETL0 XMC_ERU0, 0 #define ERU0_ETL1 XMC_ERU0, 1 #define ERU0_ETL2 XMC_ERU0, 2 #define ERU0_ETL3 XMC_ERU0, 3 #define ERU0_OGU0 XMC_ERU0, 0 #define ERU0_OGU1 XMC_ERU0, 1 #define ERU0_OGU2 XMC_ERU0, 2 #define ERU0_OGU3 XMC_ERU0, 3 #if defined(ERU1) #define ERU1_ETL0 XMC_ERU1, 0 #define ERU1_ETL1 XMC_ERU1, 1 #define ERU1_ETL2 XMC_ERU1, 2 #define ERU1_ETL3 XMC_ERU1, 3 #define ERU1_OGU0 XMC_ERU1, 0 #define ERU1_OGU1 XMC_ERU1, 1 #define ERU1_OGU2 XMC_ERU1, 2 #define ERU1_OGU3 XMC_ERU1, 3 #endif #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN24) #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN40) #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP16) #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP38) #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1200) && (UC_PACKAGE == TSSOP38) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == VQFN40) #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == TSSOP28) #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == TSSOP38) #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN24) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN40) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP16) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP28) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN24) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN40) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP16) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP38) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN24) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN40) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP16) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP28) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP38) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #endif #if (UC_DEVICE == XMC1401) && (UC_PACKAGE == LQFP64) #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #endif #if (UC_DEVICE == XMC1401) && (UC_PACKAGE == VQFN48) #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #endif #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == LQFP64) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN40) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN48) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN64) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif #if (UC_DEVICE == XMC1402) && (UC_PACKAGE == TSSOP38) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif #if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN40) #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #endif #if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN48) #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #endif #if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN64) #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #endif #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == LQFP64) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN64) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 #define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 #define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2 #define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3 #define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1 #define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 #define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 #define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 #define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif #endif /* XMC1_ERU_MAP_H */